AMPLIFIER TECHNIQUES

Vadim Ivanov
Texas Instruments, United States of America

Abstract
Operational amplifiers with high supply voltage (40V to 1000V) operate with unpredictable loads, with inductive kickbacks, shorts, often highly capacitive (in applications like piezo motors or ultrasound transmitters), large power dissipation. We will consider the gain structure and frequency compensation for any load stability without costly high voltage capacitors, techniques for precise and adjustable current limit, ganging of unlimited number of amplifiers for parallel connection, dependability and load sharing.

About the author
MSEE 1980, Ph.D. 1987, both in the USSR. Designed electronic systems and ASICs for naval navigation equipment from 1980 to 1991 in St. Petersburg, Russia and mixed signal ASICs for sensors, GPS/GLONASS receivers and for  motor control between 1991 and 1995.

Joined Burr Brown, now Texas Instruments, Tucson, in 1996, where worked on the operational, instrumentation, power amplifiers, references and switching and linear voltage regulators, and where he is currently the Operational Amplifier Technologist. Has 129 patents, with more pending, on analog circuit techniques and authored > 30 technical papers and three books: “Power Integrated Amplifiers” (Leningrad, Rumb, 1987), “Analog system design using ASICs” (Leningrad, Rumb, 1988), both in Russian, and “Operational Amplifier Speed and Accuracy Improvement”, Springer, 2004. Has been a member of ISSCC, ESSCIRC and ISCAS technical committees.

Jiawei Xu
Fudan University, People's Republic of China

Abstract
Current balance instrumentation amplifiers (CBIAs) exhibit excellent performance in terms of input impedance, noise, CMRR, and bandwidth-power efficiency. They also provide configurable gain and support different input and output common-mode voltages. These features make them well suited for use in sensor interfaces. In recent years, their linearity, dynamic range and energy efficiency has been significantly improved, and therefore CBIAs are increasingly used as the input stage of direct-digitization ADCs. This talk reviews CBIA history, principles and state-of-the-art, and provides examples of their use in biomedical and magnetic sensing, as well as in high-voltage amplifiers.

About the author
Jiawei Xu received the M.Sc. and Ph.D. degrees in electrical engineering from Delft University of Technology, Delft, The Netherlands, in 2006 and 2016, respectively.

 From 2006 to 2018, he was with imec/Holst Centre, Eindhoven, The Netherlands, where he led the IC design activities for non-invasive brain monitoring and developed several IC technologies for EEG headsets, ECG health patches, and smart wristbands. In 2018, he joined Fudan University, Shanghai, China, where his research group works on integrated circuits for wearable and implantable medical devices, precision sensor interfaces, and battery power management.

 Dr. Xu is a TPC member of ISSCC and CICC, and an Associate Editor of IEEE Transactions on VLSI Systems. He was the co-recipient of the IEEE SSCS Predoctoral Achievement Award (2014), Scientific Excellence Award of imec (2014), and ISSCC Distinguished Technical Paper Award (2019).

Thije Rooijers
Broadcom, the Netherlands

Abstract
In chopper amplifiers, the interaction between the input signal and the chopper clock may cause intermodulation distortion (IMD). This is mainly due to the amplifier’s finite bandwidth, which causes signal-dependent output spikes at the chopping transitions. These spikes, and thus the resulting IMD, can be eliminated with the help of the recently invented Fill-in technique, which involves swapping between two OTAs chopped by phase-shifted clocks. In a first prototype, two identical OTAs are chopped in quadrature, resulting in 28dB of IMD suppression. In a second prototype, a fill-in OTA is only used briefly during the chopping transitions of a main OTA. As a result, the fill-in OTA does not need to be chopped, and can also be duty-cycled to save power. Furthermore, the design achieves similar IMD performance, and due to the reduction in switching activity, 25× lower input current.

About the author
Thije Rooijers received his M.Sc. degree from Delft University of Technology, the Netherlands, in 2016. In 2024, he received his Ph.D. degree from the same university for a thesis on low-offset amplifiers with low-input current and low distortion. He is currently a senior analog and mixed-signal designer with Broadcom NL.

Dr. Rooijers received the 2018 ADI Outstanding Student Designer Award, the 2019 ProRISC Best Oral Presentation Award, the 2021 ProRISC Best Poster Award and the silver prize at the 2021 Huawei Student Design Contest. In 2021-2022 he was a recipient of the SSCS Predoctoral Achievement Award recipient. He also serves as a reviewer for the Journal of Solid-State Circuits.

Jorge Lagos
imec, Belgium

Abstract
Achieving fast, accurate and power-efficient amplification has long been one of the holy grails of switched-capacitor circuit design. About a decade ago, the emergence of the ring amplifier appeared to mark the end of this quest. Its unconventional use of a ring oscillator for amplification seemed to confer many benefits, including improved performance with technology scaling. However, many concerns were raised, especially about its robustness to PVT. In the years since, the ringamp has repeatedly evolved and changed, not only to address the aforementioned concerns but also to capitalize on the benefits of technology scaling. In this talk we will provide a review of the evolution of the ringamp, illustrating the techniques that have made it a robust building block of high-speed switched-capacitor circuits.

About the author
Jorge Lagos received the B.Sc. degree from Pontificia Universidad Católica del Perú (PUCP), Peru, in 2003, and a joint M.Sc. degree from Politecnico di Torino, Italy, Institut Polytechnique de Grenoble, France, and École Polytechnique Fédérale de Lausanne, Switzerland, in 2013. He received the Ph.D. degree in 2019 from Vrije Universiteit Brussel, Belgium, for his work on high-performance, power-efficient ADCs.

From 2004 to 2006, he was with PUCP, researching analog VLSI networks for channel decoding. From 2006 to 2011, he was with Politecnico di Torino, working on chip-level electromagnetic compatibility and system-on-chip functional test. From 2012 to 2014, he was with the Fraunhofer Institute for Integrated Circuits, Germany, focusing on front-end design for MEMS sensors. In 2018 he joined IMEC, where he is currently a Principal Member of Technical Staff conducting research in analog and mixed-signal IC design.

Dr. Lagos was a co-recipient of the 2019 ISSCC Lewis Winner Award for outstanding paper, and of the 2023 IEEE SSCS Brokaw Award for circuit elegance, for his work on ring amplifiers. He currently serves on the TPC of the IEEE Symposium on VLSI Technology and Circuits.

Xiyuan Tang
Peking University, People's Republic of China

Abstract
This talk introduces the floating inverter amplifier (FIA), a new kind of dynamic amplifier. The FIA employs current reuse and dynamic biasing, thus achieving excellent energy efficiency, as well as PVT insensitivity. Moreover, its output common-mode voltage is well controlled without the need for an explicit common-mode feedback circuit. Emerging improvements aimed at enhancing speed and performance will be introduced. Some examples including the cascoded FIA, the swing-enhancement technique, the CLS technique, covering both open- and closed-loop designs.

About the author
Dr. Xiyuan Tang received the B.Sc. degree (Hons.) from the Shanghai Jiao Tong University, Shanghai, China, in 2012, and the M.S. and Ph.D. degree from the University of Texas at Austin, Austin, TX, USA, in 2014 and 2019 respectively. He worked at Silicon Laboratories, Austin, TX from 2014 to 2017, where he was involved in RF receiver design. This was followed by a postdoc at the University of Texas at Austin from 2019-2021. He is currently an Assistant Professor at Peking University, Beijing, China.

He serves on the Technical Program Committee of ISSCC and as an associate editor of IEEE Solid-State Circuits Letters. He received the 2020 IEEE Solid-State Circuits Society Rising Stars award, the 2016 Best Paper Award of the Silicon Labs Tech Symposium, as well as a National Scholarship in 2011, and a Shanghai Scholarship in 2010.

Harijot Singh Bindra
University of Twente, the Netherlands

Abstract
Comparators are basic building blocks of data converters, memories and serial data links. In the last decade, advances in data converters have often been driven by corresponding improvements in comparator design. This talk will review the state-of-the-art in high-speed and low-noise comparator designs. It will also discuss the difficulty in finding one-size-fits-all architectures and how understanding the power-speed-noise trade-off and its impact on area are essential to designing better comparators.

About the author
Harijot Singh Bindra is an Assistant Professor at the Integrated Circuit Design Group, University of Twente, The Netherlands. He received his PhD degree (cum laude) from the University of Twente in 2019. He obtained his Bachelor’s degree (Gold Medalist) in Electronics and Communication from Punjabi University, Patiala in 2008 and Master’s degree in VLSI design from Indian Institute of Technology (IIT), Delhi in 2010. He worked as a Scientist in the Indian Space Research Organization (ISRO) from 2008-2010 and as Senior Design Engineer at Cadence Design Systems, India from 2012-2014. He served as an Associate Editor in the Transactions of Circuits and Systems – 1 (2021-23) and is currently a TPC member for European Solid-State Electronics Research Conference (ESSERC). He was awarded the VENI-2023 grant by the Dutch Research Council (NWO).